Course Overview

RTL Design & Digital Logic Fundamentals for VLSI

⏱ Duration: 30–36 Hours (2 Credit Hours) | Mode: Physical / Hybrid

Instructor

• Md. Rasedul Islam, Assistant Professor, Daffodil International University (DIU).
• Md. Emad Hossain Likhon, Lecturer, Department of Computer Science and Engineering, Daffodil International University (DIU).
• M Rifat Hossain, Lecturer, Daffodil International University (DIU) – Ex-Ulkasemi Pvt. Limited (Trained in Analog Design, IC Mask Design/Mixed-Signal Layout, and IC Physical Design; Expert in Verilog RTL Design). (Endorsed by: Professor Dr. Sheak Rashed Haider Noori, Professor & Head, Department of Computer Science and Engineering, DIU)
• Md. Ashikur Rahman, Technical Manager, Design Verification & RTL, SILICONOVA LIMITED
• Akash Ghosh, Sr. Engineer, Design Verification & RTL, SILICONOVA LIMITED

Course Description 

This technical micro-credential course builds a strong, practical foundation in Digital Logic Design (DLD) and Register-Transfer-Level (RTL) coding using industry-standard hardware description languages (Verilog/VHDL). Designed as an essential feeder course for the semiconductor industry, it equips participants with hands-on skills to design, code, simulate, and verify combinational, sequential, and finite state machine (FSM) digital circuits, serving as a direct stepping stone into VLSI frontend and backend engineering careers.

Evidence of Demand 

Foundational digital logic and RTL design skills are a prerequisite for nearly all VLSI frontend and backend career tracks. However, many engineering students and fresh graduates lack this working knowledge at entry, creating a critical preparatory competency gap before they can join advanced semiconductor training or industry roles. Through industry consultation and job-market analysis, this course has been specifically identified as a foundational feeder program for learners aiming to enter advanced BSIA–SICIP semiconductor workforce development programs (such as Advanced Physical Design: RTL to GDSII and DFT and Verification Engineering for ASIC Designers), both of which require working RTL and digital-design proficiency upon entry.

Course Objectives

This course aims to:

• Build a strong foundation in Digital Logic Design (DLD) and Register-Transfer-Level (RTL) coding using industry-standard hardware description languages (Verilog/VHDL).
• Familiarize learners with semiconductor physics, CMOS logic gates, and gate-level timing and performance trade-offs.
• Develop practical competencies in designing combinational logic, sequential memory systems, and Finite State Machines (FSMs).
• Train participants to write synthesizable RTL code, construct testbenches, and perform waveform-based functional verification to prepare for VLSI design careers.

Course Content

• Module 1: Semiconductor & CMOS Fundamentals – MOSFET Device Physics, CMOS Logic Gates, and CMOS Inverter (Concept lecture and logic simplification exercises).
• Module 2: Gate-Level Performance & Timing Analysis – RC Delay Models, Power & Speed Trade-offs (Circuit design & simulation exercises).
• Module 3: Combinational Logic Circuit Design – Karnaugh Maps, Boolean simplification, Adders, subtractors, multiplexers, demultiplexers, encoders, and decoders (Circuit design & simulation exercises).
• Module 4: Sequential Logic & Memory Systems – Bistable Circuits, Timing Constraints, Registers & Counters (Hands-on sequential circuit lab).
• Module 5: Finite State Machines (FSM) — Design and Implementation – Control logic state diagrams and implementation (FSM design workshop).
• Module 6: Introduction to Verilog/VHDL — Syntax, Data Types, and Constructs – Hardware description fundamentals (HDL coding lab).
• Module 7: RTL Coding Practices — Writing Synthesizable Code – Industry coding standards for hardware synthesis (Guided synthesizable-code exercises).
• Module 8: Simulation and Functional Verification Basics – Testbenches and Waveform Analysis (Testbench writing & waveform analysis lab).
• Module 9: Capstone — Design, Code, and Simulate a Simple Digital Module – End-to-end digital module implementation from specification to verified functionality (Capstone project).

Practical

• Circuit Design & SPICE Simulation Labs: Hands-on logic simplification, RC delay modeling, combinational circuit design, and sequential register/counter evaluation using SPICE simulation tools.
• FSM Design Workshop: Practical state-machine architecture planning and control logic implementation.
• HDL & Synthesizable RTL Coding Labs: Writing structured, synthesizable Verilog/VHDL code in professional development environments.
• Functional Verification & Capstone Project: Writing self-checking testbenches, analyzing simulation waveforms, and completing an end-to-end digital module design from specification to verified functionality.

Learning Outcomes

After completing the course, participants will be able to:

• Explain Semiconductor & CMOS Fundamentals.
• Explain Gate-Level Performance & Timing Analysis.
• Design combinational circuits and sequential circuits.
• Design and implement finite state machines (FSMs) for control logic.
• Write RTL code in Verilog/VHDL using correct syntax and synthesizable coding practices.
• Complete a capstone project — design, code, and simulate a digital module from specification to verified functionality.

Target Audience & Requirements

• Target Audience:
• Undergraduate students and fresh graduates in EEE, ECE, CSE, ICE, or RME interested in entering VLSI and semiconductor design careers.
• Entry Requirements:
• Undergraduate student or graduate in EEE, ECE, CSE, ICE, RME, or a related engineering discipline.
• Basic familiarity with introductory electronics and computer operation (serves as an entry-level preparatory course for advanced VLSI tracks).

Career Pathways

After completing this micro-credential, learners may:

• Apply for entry-level semiconductor roles such as Junior RTL Design Engineer, Digital Logic Design Intern, Trainee Engineer (IC Physical Design), Trainee Engineer (IC Mask Design), Trainee Engineer (Design Verification - DV), VLSI Physical Design Trainer, or VLSI Layout Design Trainer.
• Progress directly into Advanced Micro-Credentials and specialized industry tracks, including BSIA–SICIP's Advanced Physical Design: RTL to GDSII and DFT and Verification Engineering for ASIC Designers.

Tools & Resources

• Facilities & Equipment:
• FPGA and VLSI simulation laboratory access.
• Computers configured with Verilog/VHDL development environments.
• Tools, Instruments & Software:
• HDL Simulation Tools: Xilinx Vivado, ModelSim, Questa, or equivalent academic-licensed simulators.
• SPICE Simulation Software: LTSpice, QSpice, or equivalent circuit simulators.
• Learning Materials:
• Course syllabus, lecture slides, logic simplification worksheets, sample RTL design exercises, and functional verification testbenches.

Assessment Criteria

Aligned with Course Learning Outcomes (LO1–LO6):

• Hands-on Lab & Coding Exercises across Modules 1–8 (Assesses LO1–LO5) – 50%
• Capstone Project: Digital Module Design, Code & Simulation Report in Module 9 (Assesses LO6) – 40%
• Class Participation & Engagement (Supports All LOs) – 10% (Recommended Benchmarks: Minimum 80% attendance and minimum 60% overall assessment pass score)

Financial Information, Remuneration & Certification

• Tentative Course Fee: BDT 3,000
• Certification: Micro-Credential Certificate (2 Credit Hours) issued by DIU Micro-Credentials Academy (DIU-MCA)